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pa ckage symbol 9/6/05 p age 1 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers description optologic is the ?st family of truly logic compatible optically coupled logic interface gates. the family consists of four device types offering lsttl to ttl and lsttl to cmos interfacing. each of these interfacing functio ns is available as a buffer (a=b), or as an inverter (a=b ). the lsttl input compatibility is provided by an input integrated circuit, with industry standard logic levels. this input ampli ?r ic s witches a temperature compensated current source driving a high speed 850 nm algaas led emitter. this novel integration scheme eliminates ctr degradation over time and temperature. the emitter is optically coupled to an integrated photodetector/high-gain, high-speed output ampli?r ic. the superior 15kv/? common-mode noise rejection is ensured through the use of an optically transparent noise shield. the ttl compatible output has a totem-pole with a fan-out of 10. the cmos compatible output has an open collector schottky- clamped transistor that interfaces to any cmos logic between 4.5 and 15 volts. the 74ol6010/11 may also by used to drive power mosfets or transistors up to 15 volts. the optologic coupler family typically offers propagation of delays of 60 ns and can support 15 mbaud data communication. the two input chips and the output chip are assembled in a 6-pin dip high insulation voltage plastic package. fairchilds propr ietary optoplanar construction provides a withstand test voltage of 5300 vrms (1 minute). 6 1 6 1 6 1 buffer inverter features industry ?st lsttl to ttl and lsttl to cmos complete logic-to-logic optocoupler incorporates led drive circuitry ?use as logic gate ? ery high speed choice of buffer or inverter choice of ttl or cmos compatible output up to 15 volts ? an-out of 10 ttl loads, fan-in 1 lsttl load internal noise shield ?very high cmr of ?5 kv/? ul recognized (file #e90700) same noise immunity as lsttl/ttl. applications ? r ansmission line interface ?receiver and driver excellent as bridged receiver in fast lan highways bus interface logic family interface with ground loop noise elimination high speed ac/dc voltage sensing ? ri v er for power semiconductor devices ? ev el shifting replaces fast pulse transformers
9/6/05 p age 2 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers pin configuration 1-v cci (input v cc ) 6-v cco (output v cc ) 2-v in (data in) 5-v o (data out) 3-gnd, (input gnd) 4-gnd o (output gnd) device configuration pa rt number logic compatibility logic function output con?uration input output 74ol 6000 lsttl ttl buffer totem pole 74ol 6001 lsttl ttl inverter totem pole 74ol 6010 lsttl cmos buffer open collector 74ol 6011 lsttl cmos inverter open collector 22 k ? typ. input vcc gnd lsttl input circuit vcc 150 ? typ. ttl output circuit gnd output vcc r gnd cmos output circuit output l all inputs 74ol6000/01 output 74ol6010/11 output
9/6/05 p age 3 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers schematic lstll to ttl buffer noise shield 1 2 3 74 ol 6000 6 5 4 lstll to ttl inverter noise shield 1 2 3 74 ol 6001 6 5 4 lstll to cmos buffer noise shield 1 2 3 74 ol 6010 6 5 4 lstll to cmos inverter noise shield 1 2 3 74 ol 6011 6 5 4
9/6/05 p age 4 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers *all typical values are at t a =25? electrical characteristics (t a = 0? to 70? unless otherwise speci?d) p arameter symbol min typ* max units t est conditions notes 74ol6000 74ol6001 74ol6000/01 ttl output 74ol6000/01 input supply voltage v cci 4.5 5.0 5.5 v 1 output supply voltage v cco 4.5 5.0 5.5 v 1 high-level input voltage v ih 2.0 v 1 low-level input voltage v il 0.8 v 1 input clamp voltage v ik -1.2 v v cci = 4.5 v, i i = -18 ma 1 high-level input current i ih 1.0 40.0 ? v cci = 5.5 v, v ih = 4.5 v 1 low-level input current i il -200.0 -400.0 ? v cci = 5.5 v, v il = 0.4 v 1 input supply current (high) i ccih 10.0 14.0 ma v cci = 5.5 v, v in = v ih 1 input supply current (low) i ccil 10.0 14.0 ma v cci = 5.5 v, v in = v il 1 high-level output voltage v oh 2.4 3.0 v v in = 2.0 v v in = 0.8 v v cci = 4.5 v, v cco = 4.5 v, i oh = -400 ma 1 low-level output voltage v ol 0.3 0.6 vv in = 0.8v v in = 2.0v v cci = 4.5 v, v cco = 4.5 v, i ol = 16 ma 1 0.5 v cci = 4.5 v, v cco = 4.5 v, i ol = 4 ma high-level output current i oh -8.0 -10.0 ma v in = v ih v in = v il v cci = 4.5 v, v cco = 4.5 v, v oh = 2.4 v 1 low-level output current i ol 16.0 ma v in = 0.8 v v in = 2.0v v cci = 4.5 v, v cco = 4.5 v, v ol = 0.6 v 1 short-circuit output current i os -5.0 -25.0 -40.0 ma v in = v ih v in = v il v cci = 5.5 v, v cco = 5.5 v, 1 output supply current (high) i ccoh 9.0 15.0 ma v in = v ih v in = v il v cci = 5.5 v, v o = v oh , v cco = 5.5 v 1 output supply current (low) i ccol 8.0 12.0 ma v in = v il v in = v ih v cci = 5.5 v, v o = v ol , v cco = 5.5 v 1 switching characteristcs (t a = 25? unless otherwise speci?d) p arameter symbol min typ max units test conditions fig. notes ttl output 74ol6000/01 v cci = 5 v, v cco = 5 v propagation delay time for output low level t phl 60 100 ns 15, 17 1 propagation delay time for output high level t plh 70 100 ns 15, 17 1 output rise time for output high level t r 45 n 15, 17 1 output fall time for output low level t f 5n s 15, 17 1
9/6/05 p age 5 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers *all typical values are at t a =25? electrical characteristics (t a = 0? to 70? unless otherwise speci?d) p arameter symbol min typ* max units t est conditions notes 74ol6010 74ol6011 74ol6010/11 cmos output 74ol6010/11 input supply voltage v cci 4.5 5.0 5.5 v 1 output supply voltage v cco 4.5 15.0 v 1,3 high-level input voltage v ih 2.0 v 1 low-level input voltage v il 0.8 v 1 input clamp voltage v ik -1.2 v v cci = 4.5 v, i i = -18 ma 1 high-level input current i ih 1.0 40.0 ? v cci = 5.5 v, v ih = 4.5 v 1 low-level input current i il -200.0 -400.0 ? v cci = 5.5 v, v il = -0.4 v 1 input supply current (high) i ccih 10.0 14.0 ma v cci = 5.5 v, v in = v ih 1 input supply current (low) i ccil 10.0 14.0 ma v cci = 5.5 v, v in = v il 1 low-level output voltage v ol 0.4 0.6 vv in = 0.8v v in = 2.0v v cci = 4.5 v, v cco = 4.5 v, i ol = 16 ma 1 0.5 v cci = 4.5 v, v cco = 4.5 v, i ol = 4 ma high-level output current i oh 1.0 100.0 ? v in = v ih v in = v il v cci = 4.5 v, v oh = 15 v, v cco = 4.5 - 15 v 1 low-level output current i ol 16.0 ma v in = 0.8 v v in = 2.0v v cci = 4.5 v, v ol = 0.6v, v cco = 4.5 - 15 v 1 output supply current (high) i ccoh 9.0 12.0 ma v in = v ih v in = v il v cci = 5.5 v, v o = v oh , v cco = 4.5 v 1 11.0 18.0 v cci = 5.5 v, v o = v ol , v cco = 15 v output supply current (low) i ccol 8.0 12.0 ma v in = v il v in = v ih v cci = 5.5 v, v o = v ol , v cco = 4.5 v 1 11.0 18.0 v cci = 5.5 v, v o = v ol , v cco = 15 v switching characteristcs (t a = 25? unless otherwise speci?d) p arameter symbol min typ max units test conditions fig. notes ttl output 74ol6010/11 v cci = 5 v, v cco = 5 v, r l = 470 ? propagation delay time for output low level t phl 60 120 ns 15, 18 1 propagation delay time for output high level t plh 100 180 ns 15, 18 1 output rise time for output high level t r 50 ns 15, 18 1 output fail time for output low level t f 5n s 15, 18 1
9/6/05 p age 6 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers absolute maximum ratings (t a = 25? unless otherwise speci?d) p arameter symbol device value units tot al device storage temperature t stg all -55 to +125 ? operating temperature t opr all 0 to +70 ? lead solder temperature t sol all 260 for 10 sec ? po w er dissipation p d all 350 mw emitter input supply voltage v cci all 7 v input voltage v in all 7 v detector av erage output current i o (avg) all 40 ma output supply voltage v cco 74ol6000/01 7 v 74ol6010/11 18 output voltage v o 74ol6000/01 7 v 74ol6010/11 18 electrical characeristics (t a = 0? to 70? unless otherwise speci?d) p arameter symbol min typ max units test conditions fig. notes 74ol6000/01/10/11 common mode transient immunity at logic high level output cm h 5000 15000 v/? v cci = 5 v, v cco = 5 v, v cm = 50 vp-p 16, 19 common mode transient immunity at logic low level output cm l -5000 -15000 v/? 16, 19 common mode coupling capacitance c cm 0.005 pf capacitance (input-output) c i-o 0.7 pf vi-o = 0, f = 1 mhz 2 withstand insulation test voltage v iso 5300 vrms t a = 25?, t = 1 min, i i-o 1ma 2 insulation resistance r iso 10 11 ? v i-o = 500 vdc 2
9/6/05 p age 7 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers -200 -300 0 100 -100 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 1. input current vs. ambient temperature i i - input current ( a) v cci = 5.5v v ih = 4.5v v il = 0.4v 15 14 13 12 11 10 9 8 7 6 5 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 2. input supply current vs. ambient temperature i cci - input supply current (ma) i ccih - 74 ol 6000-6010 i ccil - 74 ol 6001-6011 i ccih - 74 ol 6001-6011 i ccil - 74 ol 6000-6010 v cci = 5.5v 3 0 9 12 15 6 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 3. output supply current vs. ambient temperature figure 4. output current vs. ambient temperature i cco - output supply current (ma) -20 -30 -10 20 10 30 50 40 60 0 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) i o - output supply current (ma) i ih i il v cci = 5.5v v cco = 15v v cci = 5.5v v cco = 5.5v 74 ol 6010/6011 v cci = 5.5v v cco = 5.5v 74 ol 6000/6001 74 ol 6010/6011 i ccoh i ccol i ccoh i ccol i ccoh i ccol (74 ol 6000/6001) i oh i ol v cci = 4.5v v cco = 4.5v v ol = 0.6v v oh = 2.4v 1 0 3 4 5 2 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 5. high-level output voltage vs. ambient temperature figure 6. low-level output voltage vs. ambient temperature v oh - high-level output voltage (v) 0.1 0.2 0.3 0.4 0.5 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) v ol - low-level output voltage (v) v cci = 4.5v v cco = 4.5v i oh = -400 a @ i ol = 16ma @ i ol = 4ma v cci = 4.5v v cco = 4.5v
9/6/05 p age 8 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers 1 0 3 4 5 2 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 7. 74 ol 6010/11 leakage current vs. ambient temperature i oh - leakage current ( a) v ccin = 4.5v v cco = 15v v out = 15v 200 100 50 10 5 1 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 8. 74 ol 6000/01 switching times vs. ambient temperature switching time (ns) t f t f 5 1 50 100 200 10 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( ?c) figure 9. 74 ol 6010/11 switching times vs. ambient temperature figure 10. common mode rejection vs. common mode voltage switching time (ns) 1 2 5 4 6 8 7 9 10 11 3 0 500 1000 15000 2000 2500 v cm - common mode transient cm - common mode transient immunity (kv/ s ) 2 0 6 8 10 12 4 456789 10 11 12 13 14 15 v cc - supply voltage ( v) figure 11. supply current vs. supply voltage figure 12. power dissipation vs. ambient temperature i cc - supply current (ma) 0 100 200 300 456789 10 11 12 13 14 15 v cco - output supply voltage (v ) p t - total package power dissipation (mw) v cco = 5v v cco = 15v v cci = 5v r l = 470 ? p.w = 200ns period = 1 s maximum allowable power dissipation @ t a = 25?c t plh t phl t r v cci = 5.0v v cco = 5.0v p.w = 200ns period = 1 s t plh t plh t r t r t f t f t phl v cco = 5v v cco = 5v v oh = 2v v ol = 0.8v r l = 470 ? (74 ol 6010/6011) i cc v cco range for 74 ol 6000/6001 i cco @t a = 55?c @t a = 70?c @t a = 85?c v cci = 5.5v v cci = 4.5v
9/6/05 p age 9 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers 1.0 0.0 1.3 1.4 1.5 1.6 1.2 1.1 -40 -20 0 20 40 60 80 100 t a - ambient temperature ( c) figure 13. input threshold voltage vs. ambient temperature figure 15. switching time test circuit v inth - input threshold voltage (v) v cci = 5.0v v cco = 5.0v 0 100 -100 -200 -300 0123456 v in - input voltage (v ) figure 14. input current vs. input voltage i in - input current ( a) v cci = 4.5v 1 2 3 6 5 4 .1 f v cci +5 v pulse gen pw =200ns period = 1 s tr = 5ns zo = 50 ? .1 f c l * v cco +5 v v o 470 ? (74 ol 6010/11) *c l = 15pf stray capacitance including probe figure 16. common mode rejection test circuit 1 2 3 + v cm - 6 5 6 .1 f h/l l/h 1k ? .1 f v cco +5 v 470 ? (74 ol 6010/11)
9/6/05 p age 10 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers note 1. the vcco and vcci supply voltages to the device must each be bypassed by a 0.1? capacitor or larger. this can be either a ceramic or solid tantalum capacitor with good high frequency characteristics. its purpose is to stabilize the operation of the high- gain ampli?rs. failure to provide the bypass will impair the dc and switching properties. the total lead length between capaci - tor and optocoupler should not exceed 1.5mm. see fig. 20. 2. device considered a two-terminal device. pins 1, 2 and 3 shorted together, and pins 4, 5 and 6 shorted together. 3. for example, assuming a v cci of 5.0v, and an ambient temperature of 70?, the maximum allowable v cco is 12.1v. 3.2v 1.3v 90% 90% 10% input, v i t plh t phl t r t f t f t r t phl 1.3v 10% 1.3v output, v o (74 ol 6000) output, v o (74 ol 6001) t plh figure 17. 74 ol 6000/01 switching times vs. ambient temperature figure 19. common mode rejection waveforms figure 20. suggested pcb lay-out 3.2v 1.3v 90% 50% 90% 50% 10% input, v i t plh t phl t r t f t f t r t phl 10% output, v o (74 ol 6010) output, v o (74 ol 6011) t plh figure 18. switching parameters 74 ol 6010/11 v cm v oh v ol 0v 50v dv cm dt v cm cm h cm l v o = 2.0v (min.) v o = 0.8v (max.) t r = input v cc bus d ata in input gnd bus output gnd bus output v cc bus .1 f 1 2 3 .1 f 6 5 4 d ata out
9/6/05 p age 11 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers note all dimensions are in inches (millimeters) pa ck ag e dimensions (through hole) pa ck ag e dimensions (surface mount) pa ck ag e dimensions (0.4 lead spacing) recommended pad layout for surface mount leadform 0.100 (2.54) typ 0.020 (0.51) min 0.350 (8.89) 0.330 (8.38) 0.270 (6.86) 0.240 (6.10) pin 1 id. 0.022 (0.56) 0.016 (0.41) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.115 (2.92) 0.300 (7.62) typ 0?to 15 0.154 (3.90) 0.100 (2.54) seating plane 0.016 (0.40) 0.008 (0.20) lead coplanarity : 0.004 (0.10) max 0.270 (6.86) 0.240 (6.10) 0.350 (8.89) 0.330 (8.38) 0.300 (7.62) typ 0.405 (10.30) max 0.315 (8.00) min 0.016 (0.40) min 2 5 pin 1 id. 0.016 (0.41) 0.008 (0.20) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) seating plane 0.165 (4.18) 4 3 0.020 (0.51) min 1 6 seating plane 0.016 (0.40) 0.008 (0.20) 0.070 (1.78) 0.045 (1.14) 0.350 (8.89) 0.330 (8.38) 0.154 (3.90) 0.100 (2.54) 0.200 (5.08) 0.135 (3.43) 0.004 (0.10) min 0.270 (6.86) 0.240 (6.10) 0.400 (10.16) typ 0 to 15 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) typ pin 1 id. 0.070 ( 1.78 ) 0.060 ( 1.52 ) 0.030 ( 0.76 ) 0.100 ( 2.54 ) 0.295 ( 7.49 ) 0.415 ( 10.54 )
9/6/05 p age 12 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers ordering information marking information option order entry identi?r description s. s surface mount lead bend sd .sd surface mount; tape and reel w. w 0.4" lead spacing 300 .300 vde 0884 300w .300w vde 0884, 0.4" lead spacing 3s .3s vde 0884, surface mount 3sd .3sd vde 0884, surface mount, tape and reel 74ol6000 v xx yy k 1 2 6 4 3 5 de?itions 1f airchild logo 2d e vice number 3 vde mark (note: only appears on parts ordered with vde option ?see order entry table) 4t wo digit year code, e.g., ?3 5t wo digit work week ranging from ?1 to ?3 6 assembly package code
9/6/05 p age 13 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers re?w pro?e (black package, no suf?) ? peak reflow temperature: 225 c (package surface temperature) ? time of temperature higher than 183 c for 60?50 seconds ? one time soldering reflow is recommended 215 c, 10?0 s 225 c peak ti me (minute) 0 300 250 200 150 100 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 te mperature ( c) time above 183 c, 60?50 sec ramp up = 3 c/sec
9/6/05 p age 14 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers 0.1 f 10 ? 1.1 k ? 100 f 1 k ? 1.1 k ? 1n6263 all diodes 2n4252 2n4252 2n2222 prsg 100 ns bit interval 1 2 250 ft. 4 8 74 ol 6000 ls04 9 5 ls04 250 ft. 11 10 250 ft. 250 ft. 6 ls04 7 ls04 buffer 6001 74 ol 6001 ol 74 6001 ol 74 6001 74 ol 1000 ft. 75 ? terminaion 3 application local area data communication systems can greately improve their noise immunity by including opotologic gates in the design. the optologic input ampli?r offers the feature of very high input impedance that permits their use as bridged line receivers. the system show above illustrates an optically isolated transmitter and multidrop receiver system. the network uses a 74ol6000 and b uffer (figure d) to isolate the transmitter and drive the 75 ? coax cable. this application uses a 1000 ft. aerial suspension 75 ? catv coax cable with data taps at 250 ft. intervals. the 74ol6001s function as bridged receivers, and as many as 30 receivers could be placed along the line with minimal signal degradation. the communication cable is terminated with a single 75 ? load at the far end of the line. signal quality "eye pattern" is shown in figures a, b and c with a 10mbaud nrz psuedo-random sequence (prs). traces 1-3 in figure a describes the transmitter section. traces 4-7 in figure b show the output of the four optologic bridged terminations. tr aces 8-11 in figure c illustrate "eye pattern" as seen at the output of a 74ls04 logic gate. the data quality is well preserv ed in that only a 30% eye closure is seen at the receiver located 1000 ft. from the transmitter. the data communication system is completely optically isolated from all of the terminal equipments. power for the transmitter (v cco ) and receiver (v cci ) is taken from an isolated power supply and distributed through a drain or messenger wire. figure a figure b figure c horizontal = 20 ns/div 42-11 horizontal = 20 ns/div 42-12, 02 horizontal = 20 ns/div 42-13/03 vertical = 2 v/div vertical = 2 v/div vertical = 2 v/div figure d buffer
life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. 9/6/05 p age 15 of 15 ?2005 fairchild semiconductor corporation ttl buffer 74ol6000 ttl inverter 74ol6001 cmos buffer 74ol6010 cmos inverter 74ol6011 lsttl to optoplanar ? high-speed logic-to-logic optocouplers
careers | sitema go datasheets, samples, buy technical information applications design center support company investors my f a home >> find products >> 74ol6011 6-pin dip lsttl to cmos inverter high-speed logic-to-logic output optocoupler general description contents ? general description ? features ? applications ? ordering information ? product status/pricing/packaging ? order samples ? safety agency certificates ? qualification support optologic? is the first family of truly logic compatible optically coupled logic interface gates. the family consists of four devices types offering lsttl to ttl and lsttl to cmos interfacing. each of these interfacing functions is available as a buffer (a=b) or as an inverter (a=b ). the lsttl input compatibility is provided by an input integrated circuit, with industry standard logic levels. this input amplifier ic switches a temperature compensated current source driving a high speed 850nm a lgaas led emitter. this novel integration scheme eliminates ctr degradation over time and temperature. the emitter is optically coupled to an integrated photodetector/high gain, high-speed output amplifier ic. the superior 15kv/s common-mode noise rejection is ensured through the use of an optically transparent noise shield. the ttl compatible output has a to tem-pole with a fan-out of 10. the cmos compatible output has an open collector schottky-clamped transistor that interfaces to any cmos logic between 4.5 and 15 volts. the 74ol6010/11 may also be used to drive power mosfets or transistors up to 15 volts. datasheet download this datasheet e - mail this datasheet this page print version related links request samples how to order products product change notices (pcns) support sales support quality and reliability design cente r pa g e 1 of 4 product folder - fair child p/n 74ol6011 - 6- p in dip lsttl to cmos inverter hi g h-s p eed lo g ic-to-lo g ic out p ut o p tocou... 16-au g -2007 mhtml:file://c:\temp\74ol6011300.mht
back to top features back to top applications back to top the optologic coupler family typically offers propagation of delays of 60ns and can support 15mbaud data communication. the two input chips and the output chip are assembled in a 6-pin dip high insulation voltage plastic package. fairchild's proprietary optoplanar? construction provides a withstand test voltage of 5300 vrms (1 minute). z industry first lsttl to ttl and lsttl to cmos complete logic-to- logic optocoupler z incorporates led drive circuitry - use a logic gate z very high speed z choice of buffer or inverter z choice of ttl or cmos compatible output up to 15 volts z fan-out of 10 ttl loads, fan-in 1 lsttl load z internal noise shield - very high cmr of 15 kv/s z ul recognized (file #e90700) z same noise immunity as lsttl/ttl z transmission line interface - receiver and driver z excellent as bridged receiver in fast lan highways z bus interface z logic family interface with ground loop noise elimination z high speed ac/dc voltage sensing z driver for power semiconductor devices z level shifting z replaces fast pulse transformers ordering information the following options can be ordered with this part: option order entry identifier description s .s surface mount lead bend pa g e 2 of 4 product folder - fair child p/n 74ol6011 - 6- p in dip lsttl to cmos inverter hi g h-s p eed lo g ic-to-lo g ic out p ut o p tocou... 16-au g -2007 mhtml:file://c:\temp\74ol6011300.mht
back to top product status/pricing/packaging back to top safety agency certificates sd .sd surface mount; tape and reel w .w 0.4" lead spacing 300 .300 vde 0884 300w .300w ovde 0884, 0.4" lead spacing 3s .3s vde 0884, surface mount 3sd .3sd vde 0884, surface mount, tape and reel product product status pb-free status package type leads packing method 74ol6011 lifetime buy dip-b 6 bulk 74ol6011300 lifetime buy dip-b 6 bulk 74ol6011300w lifetime buy dip-b 6 bulk 74ol60113s lifetime buy smdip-b 6 bulk 74ol60113sd lifetime buy smdip-b 6 tape reel 74ol6011s lifetime buy smdip-b 6 bulk 74ol6011sd lifetime buy smdip-b 6 tape reel 74ol6011w lifetime buy dip-b 6 bulk indicates product with pb -free second-level interconne ct. for more information click here. certificate agency e90700, vol. 1 (936 k) ul (1577) underwriters laboratories inc. e90700, vol. 1 (936 k) c-ul underwriters laboratories inc. 0122085 (677 k) semko semko pa g e 3 of 4 product folder - fair child p/n 74ol6011 - 6- p in dip lsttl to cmos inverter hi g h-s p eed lo g ic-to-lo g ic out p ut o p tocou... 16-au g -2007 mhtml:file://c:\temp\74ol6011300.mht
back to top qualification support click on a product for detailed qualification data back to top p01101067 (1638 k) nemko nemko fi 16812 (964 k) fimko fimko 310684 - 02 (623 k) demko demko testing & certification 1027742 (2305 k) csa canadian standa rds association 94766 (1673 k) vde vde pruf-und zertifizierungsinstitut product 74ol6011 74ol6011300 74ol6011300w 74ol60113s 74ol60113sd 74ol6011s 74ol6011sd 74ol6011w ? 2007 fairchild semiconductor products | design center | support | company news | investors | my fairchild | contact us | site index | privacy policy | site terms & conditions | standard terms & conditions o pa g e 4 of 4 product folder - fair child p/n 74ol6011 - 6- p in dip lsttl to cmos inverter hi g h-s p eed lo g ic-to-lo g ic out p ut o p tocou... 16-au g -2007 mhtml:file://c:\temp\74ol6011300.mht

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